1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a process of manufacturing a deep trench capacitor of a DRAM device.
2. Description of the Prior Art
Trench-capacitor DRAM devices are known in the art. A trench-storage capacitor typically consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor.
In general, the prior art method for fabricating a trench capacitor of a DRAM device may include several major manufacture phases as follows:
Phase 1: deep trench etching.
Phase 2: buried plate and capacitor dielectric (or node dielectric) forming.
Phase 3: first polysilicon deep trench fill and first recess etching.
Phase 4: collar oxide forming.
Phase 5: second polysilicon deposition and second recess etching.
Phase 6: collar oxide wet etching (including an extra over-etching stage).
Phase 7: third polysilicon deposition and third recess etching.
Phase 8: shallow trench isolation (hereinafter referred to as “STI”) forming.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic cross-sectional diagrams showing several intermediate steps of forming a prior art deep trench capacitor (before STI process), which are relative to the present invention. As shown in FIG. 1, a substrate 10 having a pad oxide layer 26 and a pad nitride layer 28 thereon is provided. After deep trench etching, an N+ buried plate 13 and a node dielectric layer 14 are sequentially formed in the deep trench. A first polysilicon deposition and recess process is then carried out to form a first poly layer (Poly1) at the bottom of the deep trench. A collar oxide layer 15 is formed on sidewall of the deep trench above Poly1. A second polysilicon deposition and recess process is then carried out to form a second poly layer (Poly2) atopPoly1. The collar oxide layer 15 that is not covered by Poly 2 is stripped off to expose the sidewall of the deep trench. Subsequently, as shown in FIG. 2,a third polysilicon deposition and recess process is carried out to form a third poly layer (Poly3) atopPoly2 and collar oxide layer 15. Dopants of the heavily doped Poly2 diffuse out through Poly3 to the surrounding substrate 10 to form an annular shaped buried strap out diffusion regions 16 in the following thermal process.
The above-mentioned prior art method has one drawback in that when wet etching the exposed collar oxide 15 that is not covered by the second polysilicon layer (P2), a portion of the pad oxide layer 26 is eroded due to over-etching of the collar oxide 15. As specifically indicated in the dash line circle region, the pad oxide layer 26 is slightly “pulled back” around the top of the deep trench. This causes undesired silicon corner rounding effect on the exposed silicon substrate surface around the top of the deep trench. The corner-rounding phenomenon becomes worse after going through following cleaning and oxidation processes, and may adversely affect bit line contact (CB) formation. The device performance might be degraded because the contact surface area is shrunk.